LLVM: lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp File Reference (original) (raw)

This file implements the targeting of the InstructionSelector class for AArch64. More...

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Namespaces
namespace llvm
This is an optimization pass for GlobalISel generic memory operations.
Macros
#define DEBUG_TYPE "aarch64-isel"
#define GET_GLOBALISEL_PREDICATE_BITSET
#define GET_GLOBALISEL_PREDICATES_DECL
#define GET_GLOBALISEL_TEMPORARIES_DECL
#define GET_GLOBALISEL_IMPL
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
Functions
static const TargetRegisterClass * getMinClassForRegBank (const RegisterBank &RB, TypeSize SizeInBits, bool GetAllRegSet=false)
Given a register bank, and size in bits, return the smallest register class that can represent that combination.
static bool getSubRegForClass (const TargetRegisterClass *RC, const TargetRegisterInfo &TRI, unsigned &SubReg)
Returns the correct subregister to use for a given register class.
static unsigned getMinSizeForRegBank (const RegisterBank &RB)
Returns the minimum size the given register bank can hold.
static Register createTuple (ArrayRef< Register > Regs, const unsigned RegClassIDs[], const unsigned SubRegs[], MachineIRBuilder &MIB)
Create a REG_SEQUENCE instruction using the registers in Regs.
static Register createDTuple (ArrayRef< Register > Regs, MachineIRBuilder &MIB)
Create a tuple of D-registers using the registers in Regs.
static Register createQTuple (ArrayRef< Register > Regs, MachineIRBuilder &MIB)
Create a tuple of Q-registers using the registers in Regs.
static std::optional< uint64_t > getImmedFromMO (const MachineOperand &Root)
static bool unsupportedBinOp (const MachineInstr &I, const AArch64RegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const AArch64RegisterInfo &TRI)
Check whether I is a currently unsupported binary operation:
static unsigned selectBinaryOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize.
static unsigned selectLoadStoreUIOp (unsigned GenericOpc, unsigned RegBankID, unsigned OpSize)
Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize.
static bool copySubReg (MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register SrcReg, const TargetRegisterClass *To, unsigned SubReg)
Helper function for selectCopy.
static std::pair< const TargetRegisterClass *, const TargetRegisterClass * > getRegClassesForCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Helper function to get the source and destination register classes for a copy.
static bool selectDebugInstr (MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI)
static bool selectCopy (MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
static AArch64CC::CondCode changeICMPPredToAArch64CC (CmpInst::Predicate P, Register RHS={}, MachineRegisterInfo *MRI=nullptr)
static void changeFPCCToORAArch64CC (CmpInst::Predicate CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
changeFPCCToORAArch64CC - Convert an IR fp condition code to an AArch64 CC.
static void changeFPCCToANDAArch64CC (CmpInst::Predicate CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
Convert an IR fp condition code to an AArch64 CC.
static Register getTestBitReg (Register Reg, uint64_t &Bit, bool &Invert, MachineRegisterInfo &MRI)
Return a register which can be used as a bit to test in a TB(N)Z.
static std::optional< int64_t > getVectorShiftImm (Register Reg, MachineRegisterInfo &MRI)
Returns the element immediate value of a vector shift operand if found.
static std::optional< int64_t > getVectorSHLImm (LLT SrcTy, Register Reg, MachineRegisterInfo &MRI)
Matches and returns the shift immediate value for a SHL instruction given a shift operand.
static bool getLaneCopyOpcode (unsigned &CopyOpc, unsigned &ExtractSubReg, const unsigned EltSize)
static std::pair< unsigned, unsigned > getInsertVecEltOpInfo (const RegisterBank &RB, unsigned EltSize)
Return an <Opcode, SubregIndex> pair to do an vector elt insert of a given size and RB.
static bool canEmitConjunction (Register Val, bool &CanNegate, bool &MustBeFirst, bool WillNegate, MachineRegisterInfo &MRI, unsigned Depth=0)
Returns true if Val is a tree of AND/OR/CMP operations that can be expressed as a conjunction.
static bool isSignExtendShiftType (AArch64_AM::ShiftExtendType Type)
static AArch64_AM::ShiftExtendType getShiftTypeForInst (MachineInstr &MI)
Given a shift instruction, return the correct shift type for that instruction.
static void fixupPHIOpBanks (MachineInstr &MI, MachineRegisterInfo &MRI, const AArch64RegisterBankInfo &RBI)
InstructionSelector * llvm::createAArch64InstructionSelector (const AArch64TargetMachine &, const AArch64Subtarget &, const AArch64RegisterBankInfo &)

This file implements the targeting of the InstructionSelector class for AArch64.

Todo

This should be generated by TableGen.

Definition in file AArch64InstructionSelector.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE "aarch64-isel"

◆ GET_GLOBALISEL_IMPL

#define GET_GLOBALISEL_IMPL

◆ GET_GLOBALISEL_PREDICATE_BITSET

#define GET_GLOBALISEL_PREDICATE_BITSET

◆ GET_GLOBALISEL_PREDICATES_DECL

#define GET_GLOBALISEL_PREDICATES_DECL

◆ GET_GLOBALISEL_PREDICATES_INIT

#define GET_GLOBALISEL_PREDICATES_INIT

◆ GET_GLOBALISEL_TEMPORARIES_DECL

#define GET_GLOBALISEL_TEMPORARIES_DECL

◆ GET_GLOBALISEL_TEMPORARIES_INIT

#define GET_GLOBALISEL_TEMPORARIES_INIT

◆ canEmitConjunction()

◆ changeFPCCToANDAArch64CC()

◆ changeFPCCToORAArch64CC()

changeFPCCToORAArch64CC - Convert an IR fp condition code to an AArch64 CC.

Definition at line 1318 of file AArch64InstructionSelector.cpp.

References llvm::AArch64CC::AL, llvm::AArch64CC::EQ, llvm::CmpInst::FCMP_OEQ, llvm::CmpInst::FCMP_OGE, llvm::CmpInst::FCMP_OGT, llvm::CmpInst::FCMP_OLE, llvm::CmpInst::FCMP_OLT, llvm::CmpInst::FCMP_ONE, llvm::CmpInst::FCMP_ORD, llvm::CmpInst::FCMP_UEQ, llvm::CmpInst::FCMP_UGE, llvm::CmpInst::FCMP_UGT, llvm::CmpInst::FCMP_ULE, llvm::CmpInst::FCMP_ULT, llvm::CmpInst::FCMP_UNE, llvm::CmpInst::FCMP_UNO, llvm::AArch64CC::GE, llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::LE, llvm_unreachable, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::AArch64CC::VC, and llvm::AArch64CC::VS.

Referenced by changeFPCCToANDAArch64CC().

◆ changeICMPPredToAArch64CC()

◆ copySubReg()

◆ createDTuple()

◆ createQTuple()

◆ createTuple()

Create a REG_SEQUENCE instruction using the registers in Regs.

Helper function for functions like createDTuple and createQTuple.

RegClassIDs - The list of register class IDs available for some tuple of a scalar class. E.g. QQRegClassID, QQQRegClassID, QQQQRegClassID. This is expected to contain between 2 and 4 tuple classes.

SubRegs - The list of subregister classes associated with each register class ID in RegClassIDs. E.g., QQRegClassID should use the qsub0 subregister class. The index of each subregister class is expected to correspond with the index of each register class.

Returns

Either the destination register of REG_SEQUENCE instruction that was created, or the 0th element of Regs if Regs contains a single element.

Definition at line 712 of file AArch64InstructionSelector.cpp.

References assert(), llvm::MachineIRBuilder::buildInstr(), E(), llvm::MachineIRBuilder::getMF(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), I, llvm::ArrayRef< T >::size(), and TRI.

Referenced by createDTuple(), and createQTuple().

◆ fixupPHIOpBanks()

◆ getImmedFromMO()

Definition at line 749 of file AArch64InstructionSelector.cpp.

References llvm::MachineOperand::getCImm(), llvm::getIConstantVRegValWithLookThrough(), llvm::MachineOperand::getImm(), llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::ConstantInt::getZExtValue(), llvm::MachineOperand::isCImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), MBB, MI, and MRI.

◆ getInsertVecEltOpInfo()

◆ getLaneCopyOpcode()

◆ getMinClassForRegBank()

◆ getMinSizeForRegBank()

◆ getRegClassesForCopy()

◆ getShiftTypeForInst()

◆ getSubRegForClass()

◆ getTestBitReg()

◆ getVectorShiftImm()

◆ getVectorSHLImm()

◆ isSignExtendShiftType()

◆ selectBinaryOp()

Select the AArch64 opcode for the basic binary operation GenericOpc (such as G_OR or G_SDIV), appropriate for the register bank RegBankID and of size OpSize.

Returns

GenericOpc if the combination is unsupported.

Definition at line 822 of file AArch64InstructionSelector.cpp.

◆ selectCopy()

Definition at line 1016 of file AArch64InstructionSelector.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addUse(), assert(), llvm::MachineIRBuilder::buildCopy(), llvm::BuildMI(), llvm::RegisterBankInfo::constrainGenericRegister(), copySubReg(), llvm::dbgs(), llvm::RegisterBank::getID(), getMinClassForRegBank(), getMinSizeForRegBank(), llvm::RegisterBankInfo::getRegBank(), getRegClassesForCopy(), llvm::RegisterBankInfo::getSizeInBits(), getSubRegForClass(), I, llvm::Register::isPhysical(), LLVM_DEBUG, MRI, selectCopy(), llvm::MachineOperand::setReg(), SubReg, TII, and TRI.

Referenced by selectCopy().

◆ selectDebugInstr()

◆ selectLoadStoreUIOp()

Select the AArch64 opcode for the G_LOAD or G_STORE operation GenericOpc, appropriate for the (value) register bank RegBankID and of memory access size OpSize.

This returns the variant with the base+unsigned-immediate addressing mode (e.g., LDRXui).

Returns

GenericOpc if the combination is unsupported.

Definition at line 893 of file AArch64InstructionSelector.cpp.

References isStore().

◆ unsupportedBinOp()