X86InstrInfo.cpp File Reference (original) (raw)

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Macros
#define	DEBUG_TYPE "x86-instr-info"
#define	GET_INSTRINFO_CTOR_DTOR
#define	CASE_NF(OP)
#define	VPERM_CASES(Suffix)
#define	VPERM_CASES_BROADCAST(Suffix)
#define	VPERM_CASES(Orig, New)
#define	VPERM_CASES_BROADCAST(Orig, New)
#define	CASE_ND(OP)
#define	FROM_TO_SIZE(A, B, S)
#define	GET_X86_NF_TRANSFORM_TABLE
#define	GET_X86_ND2NONND_TABLE
#define	GET_ND_IF_ENABLED(OPC)
#define	GET_EGPR_IF_ENABLED(OPC)
#define	FROM_TO(A, B)
#define	FROM_TO(FROM, TO)
#define	FROM_TO(FROM, TO)
#define	FOLD_BROADCAST(SIZE)
#define	CASE_BCAST_TYPE_OPC(TYPE, OP16, OP32, OP64)
#define	GET_INSTRINFO_HELPERS

Enumerations
enum	MachineOutlinerClass { MachineOutlinerDefault, MachineOutlinerTailCall }
	Constants defining how certain sequences should be outlined. More...

Functions
static bool	isFrameLoadOpcode (int Opcode, TypeSize &MemBytes)
static bool	isFrameStoreOpcode (int Opcode, TypeSize &MemBytes)
static bool	regIsPICBase (Register BaseReg, const MachineRegisterInfo &MRI)
	Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
static unsigned	getTruncatedShiftCount (const MachineInstr &MI, unsigned ShiftAmtOperandIdx)
	Check whether the shift count for a machine operand is non-zero.
static bool	isTruncatedShiftCountForLEA (unsigned ShAmt)
	Check whether the given shift count is appropriate can be represented by a LEA instruction.
static bool	findRedundantFlagInstr (MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr, const MachineRegisterInfo MRI, MachineInstr AndInstr, const TargetRegisterInfo TRI, const X86Subtarget &ST, bool &NoSignFlag, bool &ClearsOverflowFlag)
static unsigned	getThreeSrcCommuteCase (uint64_t TSFlags, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
	This determines which of three possible cases of a three source commute the source indexes correspond to taking into account any mask operands.
static void	commuteVPTERNLOG (MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2)
static bool	isCommutableVPERMV3Instruction (unsigned Opcode)
static unsigned	getCommutedVPERMV3Opcode (unsigned Opcode)
static bool	isConvertibleLEA (MachineInstr *MI)
static unsigned	getNewOpcFromTable (ArrayRef< X86TableEntry > Table, unsigned Opc)
static X86::CondCode	getSwappedCondition (X86::CondCode CC)
	Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).
static bool	isX87Reg (Register Reg)
	Return true if the Reg is X87 register.
static MachineBasicBlock *	getFallThroughMBB (MachineBasicBlock MBB, MachineBasicBlock TBB)
static int	getJumpTableIndexFromAddr (const MachineInstr &MI)
static int	getJumpTableIndexFromReg (const MachineRegisterInfo &MRI, Register Reg)
static bool	isHReg (Register Reg)
	Test if the given register is a physical h register.
static unsigned	CopyToFromAsymmetricReg (Register DestReg, Register SrcReg, const X86Subtarget &Subtarget)
static unsigned	getLoadStoreOpcodeForFP16 (bool Load, const X86Subtarget &STI)
static unsigned	getLoadStoreRegOpcode (Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load)
static unsigned	getStoreRegOpcode (Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
static unsigned	getLoadRegOpcode (Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
static bool	isAMXOpcode (unsigned Opc)
static bool	isDefConvertible (const MachineInstr &MI, bool &NoSignFlag, bool &ClearsOverflowFlag)
	Check whether the definition can be converted to remove a comparison against zero.
static std::pair< X86::CondCode, unsigned >	isUseDefConvertible (const MachineInstr &MI)
	Check whether the use can be converted to remove a comparison against zero.
static bool	canConvert2Copy (unsigned Opc)
static unsigned	convertALUrr2ALUri (unsigned Opc)
	Convert an ALUrr opcode to corresponding ALUri opcode.
static bool	Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
	Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined.
static bool	Expand2AddrKreg (MachineInstrBuilder &MIB, const MCInstrDesc &Desc, Register Reg)
	Expand a single-def pseudo instruction to a two-addr instruction with two k0 reads.
static bool	expandMOV32r1 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, bool MinusOne)
static bool	ExpandMOVImmSExti8 (MachineInstrBuilder &MIB, const TargetInstrInfo &TII, const X86Subtarget &Subtarget)
static void	expandLoadStackGuard (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool	expandXorFP (MachineInstrBuilder &MIB, const TargetInstrInfo &TII)
static bool	expandNOVLXLoad (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &LoadDesc, const MCInstrDesc &BroadcastDesc, unsigned SubIdx)
static bool	expandNOVLXStore (MachineInstrBuilder &MIB, const TargetRegisterInfo *TRI, const MCInstrDesc &StoreDesc, const MCInstrDesc &ExtractDesc, unsigned SubIdx)
static bool	expandSHXDROT (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
static bool	expandMOVSHP (MachineInstrBuilder &MIB, MachineInstr &MI, const TargetInstrInfo &TII, bool HasAVX)
static bool	hasPartialRegUpdate (unsigned Opcode, const X86Subtarget &Subtarget, bool ForLoadFold=false)
	Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified.
static bool	hasUndefRegUpdate (unsigned Opcode, unsigned OpNum, bool ForLoadFold=false)
static void	addOperands (MachineInstrBuilder &MIB, ArrayRef< MachineOperand > MOs, int PtrOffset=0)
static void	updateOperandRegConstraints (MachineFunction &MF, MachineInstr &NewMI, const TargetInstrInfo &TII)
static MachineInstr *	fuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII)
static MachineInstr *	fuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI, const TargetInstrInfo &TII, int PtrOffset=0)
static MachineInstr *	makeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, ArrayRef< MachineOperand > MOs, MachineBasicBlock::iterator InsertPt, MachineInstr &MI)
static bool	shouldPreventUndefRegUpdateMemFold (MachineFunction &MF, MachineInstr &MI)
static void	printFailMsgforFold (const MachineInstr &MI, unsigned Idx)
static bool	isNonFoldablePartialRegisterLoad (const MachineInstr &LoadMI, const MachineInstr &UserMI, const MachineFunction &MF)
	Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.
static SmallVector< MachineMemOperand *, 2 >	extractLoadMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static SmallVector< MachineMemOperand *, 2 >	extractStoreMMOs (ArrayRef< MachineMemOperand * > MMOs, MachineFunction &MF)
static unsigned	getBroadcastOpcode (const X86FoldTableEntry I, const TargetRegisterClass RC, const X86Subtarget &STI)
static const uint16_t *	lookup (unsigned opcode, unsigned domain, ArrayRef< uint16_t[3]> Table)
static const uint16_t *	lookupAVX512 (unsigned opcode, unsigned domain, ArrayRef< uint16_t[4]> Table)
static bool	AdjustBlendMask (unsigned OldMask, unsigned OldWidth, unsigned NewWidth, unsigned *pNewMask=nullptr)
static std::optional< ParamLoadedValue >	describeMOVrrLoadedValue (const MachineInstr &MI, Register DescribedReg, const TargetRegisterInfo *TRI)
	If DescribedReg overlaps with the MOVrr instruction's destination register then, if possible, describe the value in terms of the source register.
static void	genAlternativeDpCodeSequence (MachineInstr &Root, const TargetInstrInfo &TII, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg)

Variables
cl::opt< bool >	X86EnableAPXForRelocation
static cl::opt< bool >	NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden)
static cl::opt< bool >	PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to" " fuse, but the X86 backend currently can't"), cl::Hidden)
static cl::opt< bool >	ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static cl::opt< unsigned >	PartialRegUpdateClearance ("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden)
static cl::opt< unsigned >	UndefRegClearance ("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden)

◆ CASE_BCAST_TYPE_OPC

#define CASE_BCAST_TYPE_OPC	(	TYPE,
OP16,
OP32,
OP64 )

Value:

case TYPE: \

switch (SpillSize) { \

default: \

llvm_unreachable("Unknown spill size"); \

case 16: \

return X86::OP16; \

case 32: \

return X86::OP32; \

case 64: \

return X86::OP64; \

} \

break;

Referenced by getBroadcastOpcode().

◆ CASE_ND

◆ CASE_NF

◆ DEBUG_TYPE

#define DEBUG_TYPE "x86-instr-info"

◆ FOLD_BROADCAST

#define FOLD_BROADCAST	(	SIZE	)

Value:

LoadMI.operands_begin() + NumOps); \

return foldMemoryBroadcast(MF, MI, Ops[0], MOs, InsertPt, SIZE, \

true);

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ FROM_TO [1/3]

Value:

CASE_ND(A) NewOpcode = X86::B; \

break;

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

◆ FROM_TO [2/3]

#define FROM_TO	(	FROM,
TO )

Value:

case X86::FROM: \

return X86::TO; \

case X86::FROM##_ND: \

return X86::TO##_ND;

◆ FROM_TO [3/3]

#define FROM_TO	(	FROM,
TO )

Value:

case X86::FROM: \

return X86::TO;

◆ FROM_TO_SIZE

#define FROM_TO_SIZE	(	A,
B,
S )

◆ GET_EGPR_IF_ENABLED

#define GET_EGPR_IF_ENABLED	(	OPC	)

Value:

(STI.hasEGPR() ? OPC##_EVEX : OPC)

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

◆ GET_INSTRINFO_HELPERS

#define GET_INSTRINFO_HELPERS

◆ GET_ND_IF_ENABLED

#define GET_ND_IF_ENABLED	(	OPC	)

◆ GET_X86_ND2NONND_TABLE

#define GET_X86_ND2NONND_TABLE

◆ GET_X86_NF_TRANSFORM_TABLE

#define GET_X86_NF_TRANSFORM_TABLE

◆ VPERM_CASES [1/2]

#define VPERM_CASES	(	Orig,
New )

Value:

case X86::Orig##Z128rr: \

return X86::New##Z128rr; \

case X86::Orig##Z128rrkz: \

return X86::New##Z128rrkz; \

case X86::Orig##Z128rm: \

return X86::New##Z128rm; \

case X86::Orig##Z128rmkz: \

return X86::New##Z128rmkz; \

case X86::Orig##Z256rr: \

return X86::New##Z256rr; \

case X86::Orig##Z256rrkz: \

return X86::New##Z256rrkz; \

case X86::Orig##Z256rm: \

return X86::New##Z256rm; \

case X86::Orig##Z256rmkz: \

return X86::New##Z256rmkz; \

case X86::Orig##Zrr: \

return X86::New##Zrr; \

case X86::Orig##Zrrkz: \

return X86::New##Zrrkz; \

case X86::Orig##Zrm: \

return X86::New##Zrm; \

case X86::Orig##Zrmkz: \

return X86::New##Zrmkz;

◆ VPERM_CASES [2/2]

#define VPERM_CASES	(	Suffix	)

Value:

case X86::VPERMI2##Suffix##Z128rr: \

case X86::VPERMT2##Suffix##Z128rr: \

case X86::VPERMI2##Suffix##Z256rr: \

case X86::VPERMT2##Suffix##Z256rr: \

case X86::VPERMI2##Suffix##Zrr: \

case X86::VPERMT2##Suffix##Zrr: \

case X86::VPERMI2##Suffix##Z128rm: \

case X86::VPERMT2##Suffix##Z128rm: \

case X86::VPERMI2##Suffix##Z256rm: \

case X86::VPERMT2##Suffix##Z256rm: \

case X86::VPERMI2##Suffix##Zrm: \

case X86::VPERMT2##Suffix##Zrm: \

case X86::VPERMI2##Suffix##Z128rrkz: \

case X86::VPERMT2##Suffix##Z128rrkz: \

case X86::VPERMI2##Suffix##Z256rrkz: \

case X86::VPERMT2##Suffix##Z256rrkz: \

case X86::VPERMI2##Suffix##Zrrkz: \

case X86::VPERMT2##Suffix##Zrrkz: \

case X86::VPERMI2##Suffix##Z128rmkz: \

case X86::VPERMT2##Suffix##Z128rmkz: \

case X86::VPERMI2##Suffix##Z256rmkz: \

case X86::VPERMT2##Suffix##Z256rmkz: \

case X86::VPERMI2##Suffix##Zrmkz: \

case X86::VPERMT2##Suffix##Zrmkz:

Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().

◆ VPERM_CASES_BROADCAST [1/2]

#define VPERM_CASES_BROADCAST	(	Orig,
New )

Value:

VPERM_CASES(Orig, New) \

case X86::Orig##Z128rmb: \

return X86::New##Z128rmb; \

case X86::Orig##Z128rmbkz: \

return X86::New##Z128rmbkz; \

case X86::Orig##Z256rmb: \

return X86::New##Z256rmb; \

case X86::Orig##Z256rmbkz: \

return X86::New##Z256rmbkz; \

case X86::Orig##Zrmb: \

return X86::New##Zrmb; \

case X86::Orig##Zrmbkz: \

return X86::New##Zrmbkz;

#define VPERM_CASES(Suffix)

◆ VPERM_CASES_BROADCAST [2/2]

#define VPERM_CASES_BROADCAST	(	Suffix	)

Value:

VPERM_CASES(Suffix) \

case X86::VPERMI2##Suffix##Z128rmb: \

case X86::VPERMT2##Suffix##Z128rmb: \

case X86::VPERMI2##Suffix##Z256rmb: \

case X86::VPERMT2##Suffix##Z256rmb: \

case X86::VPERMI2##Suffix##Zrmb: \

case X86::VPERMT2##Suffix##Zrmb: \

case X86::VPERMI2##Suffix##Z128rmbkz: \

case X86::VPERMT2##Suffix##Z128rmbkz: \

case X86::VPERMI2##Suffix##Z256rmbkz: \

case X86::VPERMT2##Suffix##Z256rmbkz: \

case X86::VPERMI2##Suffix##Zrmbkz: \

case X86::VPERMT2##Suffix##Zrmbkz:

Referenced by getCommutedVPERMV3Opcode(), and isCommutableVPERMV3Instruction().

◆ MachineOutlinerClass

Constants defining how certain sequences should be outlined.

MachineOutlinerDefault implies that the function is called with a call instruction, and a return must be emitted for the outlined function frame.

That is,

I1 OUTLINED_FUNCTION: I2 --> call OUTLINED_FUNCTION I1 I3 I2 I3 ret

Call construction overhead: 1 (call instruction)
Frame construction overhead: 1 (return instruction)

MachineOutlinerTailCall implies that the function is being tail called. A jump is emitted instead of a call, and the return is already present in the outlined sequence. That is,

I1 OUTLINED_FUNCTION: I2 --> jmp OUTLINED_FUNCTION I1 ret I2 ret

Call construction overhead: 1 (jump instruction)
Frame construction overhead: 0 (don't need to return)

Enumerator
MachineOutlinerDefault
MachineOutlinerTailCall

Definition at line 10660 of file X86InstrInfo.cpp.

◆ addOperands()

◆ AdjustBlendMask()

◆ canConvert2Copy()

Returns

true if the instruction can be changed to COPY when imm is 0.

Definition at line 5691 of file X86InstrInfo.cpp.

References CASE_ND, and Opc.

◆ commuteVPTERNLOG()

◆ convertALUrr2ALUri()

Convert an ALUrr opcode to corresponding ALUri opcode.

Such as ADD32rr ==> ADD32ri

Definition at line 5709 of file X86InstrInfo.cpp.

References FROM_TO, and Opc.

◆ CopyToFromAsymmetricReg()

◆ describeMOVrrLoadedValue()

◆ Expand2AddrKreg()

◆ Expand2AddrUndef()

◆ expandLoadStackGuard()

Definition at line 6051 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addGlobalAddress(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::cast(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachinePointerInfo::getGOT(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), I, llvm::RegState::Kill, MBB, llvm::MachineInstr::memoperands_begin(), llvm::X86II::MO_GOTPCREL, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MOLoad, Reg, llvm::MachineInstr::setDebugLoc(), llvm::MachineInstr::setDesc(), and TII.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandMOV32r1()

Definition at line 5973 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::MachineInstr::getDebugLoc(), llvm::MachineInstrBuilder::getInstr(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), MBB, Reg, llvm::MachineInstr::setDesc(), TII, and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ ExpandMOVImmSExti8()

Definition at line 5991 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), assert(), llvm::X86FrameLowering::BuildCFI(), llvm::BuildMI(), llvm::MCCFIInstruction::createAdjustCfaOffset(), DL, llvm::MachineInstr::getDebugLoc(), llvm::X86Subtarget::getFrameLowering(), llvm::MachineOperand::getImm(), llvm::MachineInstrBuilder::getInstr(), llvm::TargetMachine::getMCAsmInfo(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getTarget(), llvm::X86MachineFunctionInfo::getUsesRedZone(), llvm::getX86SubSuperRegister(), llvm::TargetFrameLowering::hasFP(), I, MBB, llvm::MachineFunction::needsFrameMoves(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), TII, and llvm::MCAsmInfo::usesWindowsCFI().

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

◆ expandMOVSHP()

◆ expandNOVLXLoad()

◆ expandNOVLXStore()

◆ expandSHXDROT()

◆ expandXorFP()

◆ extractLoadMMOs()

◆ extractStoreMMOs()

◆ findRedundantFlagInstr()

Definition at line 1030 of file X86InstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::isUInt(), llvm::Register::isVirtual(), llvm::make_range(), llvm::MachineInstr::modifiesRegister(), MRI, and TRI.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

◆ fuseInst()

◆ fuseTwoAddrInst()

◆ genAlternativeDpCodeSequence()

Definition at line 10897 of file X86InstrInfo.cpp.

References llvm::Add, llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::getKillRegState(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), llvm::MachineOperand::isKill(), Opc, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), TII, and llvm::MachineInstr::untieRegOperand().

Referenced by llvm::X86InstrInfo::genAlternativeCodeSequence().

◆ getBroadcastOpcode()

Definition at line 8505 of file X86InstrInfo.cpp.

References assert(), CASE_BCAST_TYPE_OPC, llvm::X86Subtarget::getRegisterInfo(), llvm::X86Subtarget::hasAVX512(), I, llvm_unreachable, llvm::TB_BCAST_D, llvm::TB_BCAST_MASK, llvm::TB_BCAST_Q, llvm::TB_BCAST_SD, llvm::TB_BCAST_SH, llvm::TB_BCAST_SS, and llvm::TB_BCAST_W.

Referenced by llvm::X86InstrInfo::unfoldMemoryOperand(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getCommutedVPERMV3Opcode()

◆ getFallThroughMBB()

◆ getJumpTableIndexFromAddr()

◆ getJumpTableIndexFromReg()

◆ getLoadRegOpcode()

◆ getLoadStoreOpcodeForFP16()

◆ getLoadStoreRegOpcode()

◆ getNewOpcFromTable()

◆ getStoreRegOpcode()

◆ getSwappedCondition()

Assuming the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 3356 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.

Referenced by llvm::ARMBaseInstrInfo::optimizeCompareInstr(), llvm::X86InstrInfo::optimizeCompareInstr(), performCSELCombine(), PerformVCMPCombine(), and reassociateCSELOperandsForCSE().

◆ getThreeSrcCommuteCase()

◆ getTruncatedShiftCount()

◆ hasPartialRegUpdate()

◆ hasUndefRegUpdate()

◆ isAMXOpcode()

◆ isCommutableVPERMV3Instruction()

bool isCommutableVPERMV3Instruction ( unsigned Opcode)	static

◆ isConvertibleLEA()

◆ isDefConvertible()

◆ isFrameLoadOpcode()

◆ isFrameStoreOpcode()

◆ isHReg()

◆ isNonFoldablePartialRegisterLoad()

Check if LoadMI is a partial register load that we can't fold into MI because the latter uses contents that wouldn't be defined in the folded version.

For instance, this transformation isn't legal: movss (rdi), xmm0 addps xmm0, xmm0 -> addps (rdi), xmm0

But this one is: movss (rdi), xmm0 addss xmm0, xmm0 -> addss (rdi), xmm0

Definition at line 7711 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), Opc, RegSize, and TRI.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

◆ isTruncatedShiftCountForLEA()

bool isTruncatedShiftCountForLEA ( unsigned ShAmt)	inlinestatic

◆ isUseDefConvertible()

◆ isX87Reg()

◆ lookup()

◆ lookupAVX512()

◆ makeM0Inst()

◆ printFailMsgforFold()

◆ regIsPICBase()

◆ shouldPreventUndefRegUpdateMemFold()

◆ updateOperandRegConstraints()

Definition at line 7266 of file X86InstrInfo.cpp.

References llvm::dbgs(), llvm::MachineInstr::dump(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isReg(), LLVM_DEBUG, MRI, Reg, llvm::seq(), and TII.

Referenced by fuseInst(), and fuseTwoAddrInst().

◆ NoFusing

cl::opt< bool > NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"), cl::Hidden) ( "disable-spill-fusing" , cl::desc("Disable fusing of spill code into instructions") , cl::Hidden )	static

◆ PartialRegUpdateClearance

cl::opt< unsigned > PartialRegUpdateClearance("partial-reg-update-clearance", cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update"), cl::init(64), cl::Hidden) ( "partial-reg-update-clearance" , cl::desc("Clearance between two register writes " "for inserting XOR to avoid partial " "register update") , cl::init(64) , cl::Hidden )	static

◆ PrintFailedFusing

◆ ReMatPICStubLoad

cl::opt< bool > ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) ( "remat-pic-stub-load" , cl::desc("Re-materialize load from stub in PIC mode") , cl::init(false) , cl::Hidden )	static

◆ UndefRegClearance

cl::opt< unsigned > UndefRegClearance("undef-reg-clearance", cl::desc("How many idle instructions we would like before " "certain undef register reads"), cl::init(128), cl::Hidden) ( "undef-reg-clearance" , cl::desc("How many idle instructions we would like before " "certain undef register reads") , cl::init(128) , cl::Hidden )	static